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RF3854
LOW NOISE, MULTI-MODE, QUAD-BAND, QUADRATURE MODULATOR AND PA DRIVER
RoHS Compliant & Pb-Free Product Package Style: QFN, 24-Pin, 4x4
MODE B MODE A I SIG N I SIG P
VCC1
24 VCC2 1
23
22
21
20
19 18 RF OUT WB P RF OUT WB N RF OUT HB P RF OUT HB N RF OUT LB P RF OUT LB N
Features
W-CDMA High/Mid/Low Power Modes Quad-Band Direct Quadrature Modulator Variable Gain PA Drivers GMSK Bypass Amplifiers LO Frequency Doubler and Divider Baseband Filtering Qualified to Infrastructure Standards
LO HB P 2
Note: The die flag is the chip's main ground.
GND 17 16 15 14 13 12 GC
LO HB N 3
DIV 2
+45 -45
LO LB P 4
Flo x2
+45 -45
LO LB N 5
Mode Control and Biasing
Power Control
MODE C 6 7 MODE D 8 Q SIG N 9 Q SIG P 10 VREF 11 GC DEC
Applications
CDMA, GSM, and UMTS Basestation Architecture ISM Transceivers Broadband Fixed Wireless Access and Wireless Local Loop GMSK, QPSK, DQPSK, QAM Modulation
Functional Block Diagram
Product Description
The RF3854 is a low noise, multi-mode, quad-band direct I/Q to RF modulator and PA driver solution designed for digital modulation applications ranging from 800MHz to 2000MHz. Frequency doublers, dividers and LO buffers are included to support a variety of LO generation options. Dynamic power control is supported through a single analog input giving 90dB of power control range for the W-CDMA mode and 40dB of power control in the other two modes. Three sets of RF outputs are provided: high band and low band low noise EDGE/GMSK outputs, as well as one wideband W-CDMA output. The device is designed for 2.7V to 3.3V operation, and is assembled in a plastic, 24-pin, 4mmx4mm QFN.
Ordering Information
RF3854 RF3854PCBA-41X Low Noise, Multi-Mode, Quad-Band, Quadrature Modulator and PA Driver Fully Assembled Evaluation Board
Optimum Technology Matching(R) Applied
GaAs HBT GaAs MESFET InGaP HBT SiGe BiCMOS Si BiCMOS SiGe HBT GaAs pHEMT Si CMOS Si BJT GaN HEMT
RF MICRO DEVICES(R), RFMD(R), Optimum Technology Matching(R), Enabling Wireless ConnectivityTM, PowerStar(R), POLARISTM TOTAL RADIOTM and UltimateBlueTM are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. (c)2006, RF Micro Devices, Inc.
Rev A1 DS070313
7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
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RF3854
Absolute Maximum Ratings Parameter
Supply Voltage Storage Temperature Operating Ambient Temperature Input Voltage, any pin Input Power, any pin
Rating
-0.5 to 3.6 -40 to +150 -40 to +85 -0.5 to +3.6 +5
Unit
V C C V dBm
Caution! ESD sensitive device.
The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice. RoHS status based on EUDirective2002/95/EC (at time of this document revision).
Specification Unit Min. Typ. Max. Output Performance with Modulated Baseband Inputs Low Band EDGE 8PSK Mode (GSM850/GSM900) Mode=Low Band FLOx1 (see Control Logic Truth Table for Mode Control Settings) Parameter
Output Power
Maximum Output Power with 8PSK Modulated Signal* Maximum VGC Minimum VGC Gain Range 0 +2.5 -39 42 -37 dBm dBm dB
Condition
VCC =2.7V, T=+25C
While meeting spectral mask While meeting spectral mask Difference between output power at GC=2.0V and GC=0.2V.
Out-of-Band Emission
Spectrum Emission Mask* Frequency Spacing 200kHz 250kHz 400kHz 600kHz to 1800kHz 1800kHz to 3000kHz 3000kHz to 6000kHz >6000kHz -36 -43 -67 -73 -73 -73 -75 2 -40 4 3 -34 9 TBD TBD TBD dBc dBc dBc dBc dBc dBc dBc % dB % 30kHz BW 30kHz BW 30kHz BW 30kHz BW 100kHz BW 100kHz BW 100kHz BW 8PSK Modulation
Error Vector Magnitude
RMS* Origin Offset* Peak*
Output Noise
At FC 20MHz* Relative Noise at: Maximum Gain Absolute Noise at: Maximum Gain All Gain Settings * Not tested in Production -156 -154 dBm dBm GC=2.0V, IQ=0VP-P IQ=1.2VP-P 8PSK -156 -152 dBc/Hz dBc/Hz GC=2.0V, IQ=1.2VP-P 8PSK GC=2.0V to 1.4V
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7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Rev A1 DS070313
RF3854
Parameter
General Conditions
Local Oscillator LO LB Input Frequency RF LB Output Frequency Input Power IQ Baseband Inputs IQ Level IQ Common Mode Input Bandwidth Baseband Filter Attenuation 0.7 20 1.2 1.2 1.0 VP-P V MHz dB At 20MHz offset 824 824 -6.0 0.0 915 915 +3.0 MHz MHz dBm 8PSK Input IQ signal driven differentially and in quadrature.
Min.
Specification Typ.
Max.
Unit
Condition
Output Performance with Modulated Baseband Inputs High Band EDGE 8PSK Mode (DCS1800/PCS1900) Mode=High Band FLOx1 (see Control Logic Truth Table for Mode Control Settings)
Output Power
Maximum Output Power with 8PSK Modulated Signal* Maximum VGC Minimum VGC Gain Range -1 +1.5 -40 42 -38 dBm dBm dB While meeting spectral mask While meeting spectral mask Difference between output power at GC=2.0V and GC=0.2V. VCC =2.7V, T=+25C
Out-of-Band Emission
Spectrum Emission Mask* Frequency Spacing 200kHz 250kHz 400kHz 600kHz to 1800kHz 1800kHz to 3000kHz 3000kHz to 6000kHz >6000kHz -36 -43 -67 -73 -73 -73 -75 1.3 -37 3 3 -30 11 TBD TBD TBD dBc dBc dBc dBc dBc dBc dBc % dB % 30kHz BW 30kHz BW 30kHz BW 30kHz BW 100kHz BW 100kHz BW 100kHz BW 8PSK Modulation
Error Vector Magnitude
RMS* Origin Offset* Peak*
Output Noise
At FC 20MHz* Relative Noise at: Maximum Gain Absolute Noise at: Maximum Gain All Gain Settings * Not tested in Production -153 -151 dBm dBm GC=2.0V, IQ=0VP-P IQ=1.2VP-P 8PSK -154 -150 dBc/Hz dBc/Hz GC=2.0V, IQ=1.2VP-P 8PSK GC=2.0V to 1.4V
Rev A1 DS070313
7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
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RF3854
Parameter
General Conditions
Local Oscillator LO HB Input Frequency RF HB Output Frequency Input Power IQ Baseband Inputs IQ Level IQ Common Mode Input Bandwidth Baseband Filter Attenuation 0.7 20 1.2 1.2 1.0 VP-P V MHz dB At 20MHz offset 1710 1710 -6.0 0.0 1910 1910 +3.0 MHz MHz dBm 8PSK Input IQ signal driven differentially and in quadrature.
Min.
Specification Typ.
Max.
Unit
Condition
Output Performance with Modulated Baseband Inputs W-CDMA Mode Mode=Wideband FLOx2 (see Control Logic Truth Table for Mode Control Settings)
Output Power
Maximum Output Power with W-CDMA Modulated Signal* High Power Mode Medium Power Mode 3 -4 6 -1 dBm dBm GC=2.0V GC=1.5V Difference between output power at GC=2.0V and GC=0.2V. High Power Mode 90 dB Gain step when switching between power modes in either direction. 0.5 TBD dB dB GC=1.4V GC=TBD VCC =2.7V, T=+25C, while meeting 48dBc ALCR
Gain Range
Gain Step
High Power to Medium Power Medium Power to Low Power
Out-of-Band Emission
Adjacent Channel Leakage Power Ratio (ALCR)* Channel Spacing 5MHz 10MHz 50 65 1.4 -152 -146 -146 * Not tested in Production dBc dBc %rms dBc/Hz dBc/Hz 3.84MHz relative to channel power 3.84MHz relative to channel power 3GPP W-CDMA GC=2.0V GC=2.0V to 1.5V
Error Vector Magnitude
RMS*
Output Noise
At FC 40MHz*
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7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Rev A1 DS070313
RF3854
Parameter
General Conditions
Local Oscillator LO LB Input Frequency RF WB Output Frequency Input Power IQ Baseband Inputs IQ Level IQ Common Mode Input Bandwidth Baseband Filter Attenuation 8 10 0.8 1.2 11 VP-P V MHz dB At 40MHz offset 960 1920 -10.0 0.0 990 1980 +3.0 MHz MHz dBm 3GPP W-CDMA HQPSK, 1DPCCH+1DPDCH Input IQ signal driven differentially and in quadrature.
Min.
Specification Typ.
Max.
Unit
Condition
Output Performance with CW Baseband Inputs Wideband Mode Mode=Wideband FLOx2 (see Control Logic Truth Table for Mode Control Settings)
VGA and PA Driver
Output Power W-CDMA Modulated* Output Power CW Gain Control Voltage Range Gain Control Range Gain Control Slope 2 0.2 92 73 -48 -50 -50 -50 -42 -41 -38 -23 3rd Harmonic of Modulation Suppression at FC-3x300kHz -55 -30 -30 -30 -30 -30 -30 -30 -10 -50 5 5 8 2.0 dBm dBm V dB dB/V dBc dBc dBc dBc dBc dBc dBc dBc dBc Difference between output power at GC=2.0V and GC=0.2V Calculated between GC=1.0V and 0.5V GC=2.0V, No I/Q adjustment GC=1.5V, No I/Q adjustment GC=1.0V, No I/Q adjustment GC=0.5V, No I/Q adjustment GC=2.0V, No I/Q adjustment GC=1.5V, No I/Q adjustment GC=1.0V, No I/Q adjustment GC=0.5V, No I/Q adjustment GC=2.0V VCC =2.7V, T=+25C, LO=975MHz to 990MHz at -10dBm, IQ=540mVP-P** at 100kHz, unless otherwise noted GC=2.0V, IQ=0.8VP-P at HQPSK GC=2.0V
Modulator
Sideband Suppression * * * Carrier Suppression
Spurious Outputs
Spurious Output at Integer Multiples of FLO LB* FLO LB 4xFLO LB 6xFLO LB -60.0 -14.0 -47.0 +11.5 0 0 dBm dBm dBm dBm GC=2.0V, I/Q=540mVP-P at 100kHz FLO LB leakage Second harmonic of carrier Third harmonic of carrier I/Q=100kHz
Output Compression
Output P1dB* * Not tested in Production ** Provides the same output power as modulated signal with associated crest factor.
Rev A1 DS070313
7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
5 of 26
RF3854
Parameter
Intermodulation
Output IP3* +20 dBm GC=2.0V. Extrapolated from IM3 with two baseband tones at 90kHz and 110kHz applied differentially, in quadrature, at both I and Q inputs, each tone 400mVP-P. GC=2.0V
Min.
Specification Typ.
Max.
Unit
Condition
Intermodulation IM3 tone at FC +70kHz and FC +130kHz relative to tones at FC +90kHz and FC +110kHz
-37
dBc
-40
dBc
GC=1.5V
Output Performance with CW Baseband Inputs Low Band Mode (GSM850/GSM900) Mode=Low Band FLOx1 (see Control Logic Truth Table for Mode Control Settings)
VGA and PA Driver
Output Power 8PSK Modulated* Output Power CW * -44 Gain Control Voltage Range Gain Control Range Gain Control Slope 0.2 42 28 -36 -36 -36 -36 -36 -44 -44 * -44 -44 -40 3rd Harmonic of Modulation Suppression at FC-3x300kHz * Not tested in Production ** Provides the same output power as modulated signal with associated crest factor. -49 -30 -30 -30 -30 -30 -34 -34 -34 -34 -34 -40 0 +2.5 2.2 -1.2 -13.5 -30 -40 -37 2.0 +5 dBm dBm dBm dBm dBm dBm V dB dB/V dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Difference between output power at GC=2.0V and GC=0.2V Calculated between GC=0.5V and 1.5V GC=2.0V, No I/Q adjustment GC=1.5V, No I/Q adjustment GC=1.0V, No I/Q adjustment GC=0.5V, No I/Q adjustment GC=0.2V, No I/Q adjustment GC=2.0V, No I/Q adjustment GC=1.5V, No I/Q adjustment GC=1.0V, No I/Q adjustment GC=0.5V, No I/Q adjustment GC=0.2V, No I/Q adjustment GC=2.0V VCC =2.7V, T=+25C, LO=824MHz to 915MHz at 0dBm, IQ=800mVP-P** at 100kHz, unless otherwise noted GC=2.0V, IQ=1.2VP-P 8PSK GC=2.0V, IQ=800mVP-P at 100kHz GC=1.5V, IQ=800mVP-P at 100kHz GC=1.0V, IQ=800mVP-P at 100kHz GC=0.5V, IQ=800mVP-P at 100kHz GC=0.2V, IQ=800mVP-P at 100kHz
Modulator
Sideband Suppression * * * * Carrier Suppression
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7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Rev A1 DS070313
RF3854
Parameter
Spurious Outputs
Spurious Outputs at Integer Harmonics of 1/2xFLOHB* FLO HB (3/2)xFLO LB -62.0 -19.0 +7.0 dBm dBm dBm
Min.
Specification Typ.
Max.
Unit
FLO/2 Mode
Condition
GC=2.0V, I/Q=800mVP-P at 100kHz Second harmonic of carrier and LO leakage Third harmonic of carrier I/Q=100kHz
Output Compression
Output P1dB*
Output Performance with CW Baseband Inputs Low Band Mode (GSM850/GSM900), cont'd Mode=Low Band FLOx1 (see Control Logic Truth Table for Mode Control Settings)
Intermodulation
Output IP3* +20.0 dBm GC=2.0V. Extrapolated from IM3 with two baseband tones at 90kHz and 110kHz applied differentially, in quadrature, at both I and Q inputs, each tone 400mVP-P.
Intermodulation IM3 tone at FC +70kHz and FC +130kHz relative to tones at FC +90kHz and FC +110kHz
-48
dBc
GC=2.0V
Low Band Bypass Mode (GSM850/GSM900) Mode=Low Band Bypass (see Control Logic Truth Table for Mode Control Settings)
PA Driver
GMSK Input Power* GMSK Output Power Output Impedance* -3 5.0 0 7.5 50 -161 -159 +3 10.0 dBm dBm dBc/Hz AM+PM noise, LO=0dBm VCC =2.7V At LO LB input from a 50 source. At RF LB output
Output Noise
At FC 20MHz* * Not tested in Production ** Provides the same output power as modulated signal with associated crest factor.
Rev A1 DS070313
7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
7 of 26
RF3854
Specification Unit Min. Typ. Max. Output Performance with CW Baseband Inputs High Band Mode (DCS1800/PCS1900) Mode=High Band FLOx1 (see Control Logic Truth Table for Mode Control Settings) Parameter
VGA and PA Driver
Output Power 8PSK Modulated* Output Power CW * -44 Gain Control Voltage Range Gain Control Range Gain Control Slope 0.2 42 28 -45 -45 -45 -45 -45 -40 -40 * -40 -39 -37 3rd Harmonic of Modulation Suppression at FC-3x300kHz -50 -30 -30 -30 -30 -30 -34 -34 -33 -30 -30 -40 0 0 2.2 2 -1.6 -17.6 -30 -40 -37 2.0 +6.0 dBm dBm dBm dBm dBm dBm V dB dB/V dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Difference between output power at GC=2.0V and GC=0.2V Calculated between GC=0.5V and 1.5V GC=2.0V, No I/Q adjustment GC=1.5V, No I/Q adjustment GC=1.0V, No I/Q adjustment GC=0.5V, No I/Q adjustment GC=0.2V, No I/Q adjustment GC=2.0V, No I/Q adjustment GC=1.5V, No I/Q adjustment GC=1.0V, No I/Q adjustment GC=0.5V, No I/Q adjustment GC=0.2V, No I/Q adjustment GC=2.0V FLOx2 Mode GC=2.0V, I/Q=800mVP-P at 100kHz -70.0 -25.0 -40.0 +8.0 dBm dBm dBm dBm FLO LB leakage Second harmonic of carrier Third harmonic of carrier I/Q=100kHz
Condition
VCC =2.7V, T=+25C, LO=1710MHz to 1910MHz at 0dBm, IQ=800mVP-P** at 100kHz, unless otherwise noted GC=2.0V, IQ=1.2VP-P 8PSK GC=2.0V, IQ=800mVP-P at 100kHz GC=1.5V, IQ=800mVP-P at 100kHz GC=1.0V, IQ=800mVP-P at 100kHz GC=0.5V, IQ=800mVP-P at 100kHz GC=0.2V, IQ=800mVP-P at 100kHz
Modulator
Sideband Suppression * * * * Carrier Suppression
Spurious Outputs
Spurious Outputs at Integer Harmonics of 1/2xFLOHB FLO LB 4xFLO LB 6xFLO LB
Output Compression
Output P1dB* * Not tested in Production ** Provides the same output power as modulated signal with associated crest factor.
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7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Rev A1 DS070313
RF3854
Specification Unit Min. Typ. Max. Output Performance with CW Baseband Inputs High Band Mode (DCS1800/PCS1900), cont'd Mode=High Band FLOx1 (see Control Logic Truth Table for Mode Control Settings) Parameter
Intermodulation
Output IP3* +20 dBm GC=2.0V. Extrapolated from IM3 with two baseband tones at 90kHz and 110kHz applied differentially, in quadrature, at both I and Q inputs, each tone 400mVP-P.
Condition
Intermodulation IM3 tone at FC +70kHz and FC +130kHz relative to tones at FC +90kHz and FC +110kHz
-53
-42
dBc
GC=2.0V
Output Performance with CW Baseband Inputs Wideband Mode Mode=Wideband FLOx2 (see Control Logic Truth Table for Mode Control Settings)
VGA and PA Driver
Output Power W-CDMA Modulated* Output Power CW Gain Control Voltage Range Gain Control Range Gain Control Slope 2 0.2 92 73 -48 -50 -50 -50 -42 -41 -38 -23 3rd Harmonic of Modulation Suppression at FC-3x300kHz -55 -30 -30 -30 -30 -30 -30 -30 -10 -50 5 5 8 2.0 dBm dBm V dB dB/V dBc dBc dBc dBc dBc dBc dBc dBc dBc Difference between output power at GC=2.0V and GC=0.2V Calculated between GC=1.0V and 0.5V GC=2.0V, No I/Q adjustment GC=1.5V, No I/Q adjustment GC=1.0V, No I/Q adjustment GC=0.5V, No I/Q adjustment GC=2.0V, No I/Q adjustment GC=1.5V, No I/Q adjustment GC=1.0V, No I/Q adjustment GC=0.5V, No I/Q adjustment GC=2.0V VCC =2.7V, T=+25C, LO=975MHz to 990MHz at -10dBm, IQ=540mVP-P** at 100kHz, unless otherwise noted GC=2.0V, IQ=0.8VP-P at HQPSK GC=2.0V
Modulator
Sideband Suppression * * * Carrier Suppression
Spurious Outputs
Spurious Output at Integer Multiples of FLO LB* FLO LB 4xFLO LB 6xFLO LB -60.0 -14.0 -47.0 +11.5 0 0 dBm dBm dBm dBm GC=2.0V, I/Q=540mVP-P at 100kHz FLO LB leakage Second harmonic of carrier Third harmonic of carrier I/Q=100kHz
Output Compression
Output P1dB* * Not tested in Production ** Provides the same output power as modulated signal with associated crest factor.
Rev A1 DS070313
7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
9 of 26
RF3854
Parameter
Intermodulation
Output IP3* +20 dBm GC=2.0V. Extrapolated from IM3 with two baseband tones at 90kHz and 110kHz applied differentially, in quadrature, at both I and Q inputs, each tone 400mVP-P. GC=2.0V
Min.
Specification Typ.
Max.
Unit
Condition
Intermodulation IM3 tone at FC +70kHz and FC +130kHz relative to tones at FC +90kHz and FC +110kHz
-37
dBc
-40
dBc
GC=1.5V
High Band Bypass Mode (DCS1800/PCS1900) Mode=High Band Bypass (see Control Logic Truth Table for Mode Control Settings)
PA Driver
GMSK Input Power* GMSK Output Power Output Impedance* -3 4.0 0 6.8 50 -161 -159 +3 9.0 dBm dBm dBc/Hz AM+PM noise, LO=0dBm VCC =2.7V At LO LB input from a 50 source. At RF LB output
Output Noise
At FC 20MHz* * Not tested in Production ** Provides the same output power as modulated signal with associated crest factor.
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7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Rev A1 DS070313
RF3854
Parameter General Specifications
Operating Range
Supply Voltage Temperature 2.7 -40 3.3 +85 V C Refer to Logic Control Truth Table for Mode Control Pin Voltages. Sleep Wideband FLOx1 (high power) * (medium power) * (low power) * Wideband FLOx2 (high power) (medium power) (low power) High Band FLOx2 Low Band FLO/2 High Band Bypass Low Band Bypass High Band FLOx1 Low Band FLOx1 <1 114 85 89 54 63 42 110 84 80 53 54 41 72 82 23 22 76 74 0 1.4 <1.0 800 1600 50 1000 2000 0.4 VCC 10 A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V A MHz MHz Externally matched CMOS inputs GC=2.0V GC=2.0V GC=2.0V GC=0.2V GC=2.0V GC=0.2V GC=2.0V. See Note 1. GC=0.2V. See Note 1. GC=2.0V GC=0.2V GC=2.0V GC=0.2V GC=2.0V. See Note 1. GC=0.2V. See Note 1. GC=2.0V GC=2.0V
Min.
Specification Typ.
Max.
Unit
Condition
Current Consumption
Logic Levels
Input Logic 0 Input Logic 1 Logic Pins Input Current
LO Input Ports
LO LB Input Frequency Range LO HB Input Frequency Range Input Impedance
Note 1: In low power mode it is recommended that the IQ level be reduced to 0.4VP-P. If IQ level is >0.4VP-P, this mode should be used for WCDMA TX power levels below -20dBm (measured at antenna).
Rev A1 DS070313
7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
11 of 26
RF3854
Parameter
I/Q Baseband Inputs
Baseband Input Voltage Baseband Input Level EDGE W-CDMA GMSK Baseband Input Impedance Input Bandwidth EDGE W-CDMA Baseband Filter Attenuation EDGE W-CDMA Baseband Input DC Current Gain Control Gain Control Voltage Gain Control Impedance 0.2 10 2.2 V k 20 10 -10 0 10 dB dB A At 20MHz At 40MHz 0.7 8.0 1.0 11.0 MHz MHz 100k||1pF 1.2 0.8 1.0 VP-P VP-P VP-P Differential 1DPCCH+1DPDCH. See Note 1. Differential Measured at 100kHz 1.15 1.25 V Common mode voltage
Min.
Specification Typ.
Max.
Unit
Condition
Output Performance with BTS waveform: W-CDMA test model I, 64 DPCH Wideband Mode Mode=Wideband FLOx1 (see Logic Control Truth Table for Mode Control Settings)
Frequency Output Power Adjacent Channel Power Noise Floor 2110 -14 -65 -150 2170 MHz dBm dBc dBm/Hz ACP measured in 3.84MHz channel, 5MHz offset from carrier 40MHz offset from carrier VCC =3.3V, VGC =1.6V
Note 1: In low power mode it is recommended that the IQ level be reduced to 0.4VP-P. If IQ level is >0.4VP-P, this mode should be used for WCDMA TX power levels below -20dBm (measured at antenna).
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7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Rev A1 DS070313
RF3854
Pin 1 Function VCC2 Description
Supply for LO buffers, frequency doubler and dividers.
Interface Schematic
VCC2 Modulator and VGA
2
LO HB P
High band local oscillator input (1800MHz). In "low band FLO/2" modes the signal (LOHBP-LOHBN) undergoes a frequency division of 2 to provide the low band LO signal for the modulator. In "high band FLOx1" modes the signal (LOHBP-LOHBN) is used as the high band LO signal for the modulator. In "high band bypass" a modulated DCS1800/PCS1900 signal (LOHBPLOHBN) is switched into the RF signal path. The modulator is disabled and the signal is routed to the RFOutHb outputs through a differential PA driver amplifier. The LOHBP input is AC-coupled internally. The noise performance, carrier suppression at low output powers and sideband suppression all vary with LO power. The optimum LO power is between -3dBm and +3dBm. The device will work with LO powers as low as -20dBm however this is at the expense of higher phase noise in the LO circuitry and poorer sideband suppression. The input impedance should be externally matched to 50. The port can be driven either differentially or single ended. The port impedance does not vary significantly between active and power down modes.
VCC
LO HB P
LO HB N
3
LO HB N
4
LO LB P
The complementary LO input for both LOHBP LO signals. See pin 2. In any of the modes the LOHB input may be driven either single ended or differentially. If the LO is driven single ended then the PCB board designer can ground this pin. It is recommended that if this pin is grounded that it is kept isolated from the GND1 pin and the die flag ground. All connections to any other ground should be made through a ground plane. Poor routing of this ground signal can significantly degrade the LO leakage performance. Low band local oscillator input (900MHz). In "wideband FLOx2" and "high band FLOx2" modes the signal (LOLBPLOLBN) is doubled in frequency to provide the LO signal for the modulator. V In "Low band FLOx1" modes the signal (LOLBP-LOLBN) is used as the LO signal for the modulator. In "Low band Bypass" a modulated GSM900 signal (LOLBP-LOLBN) is switched into the RF signal path. The modulator is disabled and the signal is routed to the RFOutLb outputs through a differential PA driver amplifier. This LOLBP input is AC-coupled internally. The noise performance, carrier suppression at low output powers and side- LO LB P band suppression performance are functions of LO power. The optimum LO power is between -3dBm and +3dBm. The device will work with LO powers LO LB N as low as -20dBm however this is at the expense of higher noise performance at high output powers and poorer sideband suppression. The input impedance should be externally matched to 50. The port impedance does not vary significantly between active and powered modes.
CC
5
LO LB N
The complementary LO input for both LOLBP LO signals. In any of the modes the LOLB input may be driven either single ended or differentially. If the LO is driven single ended then the PCB board designer can ground this pin. It is recommended that if this pin is grounded that it is kept isolated from the GND1 pin and the die flag ground. All connections to any other ground should be made through a ground plane. Poor routing of this GndLO signal can significantly degrade the LO leakage performance.
See pin 4.
Rev A1 DS070313
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RF3854
Pin 6 Function MODE C Description
Chip enable control pin. See the Logic Truth table. CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to VCC.
Interface Schematic
V
CC2
7 8
MODE D Q SIG N
Mode control pin. See the Logic Truth table. CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to VCC. Quadrature Q channel negative baseband input port. Best performance is achieved when the QSIGP and QSIGN are driven differentially with a 1.2V common mode DC voltage. The recommended differential drive level (VQSIGP -VQSIGN) is 1.2VP-P for EDGE, 0.8VP-P for WCDMA modulation and 1.0VP-P for GMSK modulation. This input should be DC-biased at 1.2V. In sleep mode an internal FET switch is opened, the input goes high impedance and the modulator is debiased. Phase or amplitude errors between the QSIGP and QSIGN signals will result in a common-mode signal which may result in an increase in the even order distortion of the modulation in the output spectrum. DC offsets between the QSIGP and QSIGN signals will result in increased carrier leakage. Small DC offsets may be deliberately applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to cancel out the LO leakage. The optimum corrective DC offsets will change with mode, frequency and gain control. Common-mode noise on the QSIGP and QSIGN should be kept low as it may degrade the noise performance of the modulator. Phase offsets from quadrature between the I and Q baseband signals results in degraded sideband suppression. Quadrature Q channel negative baseband input port. See pin 8. Voltage reference decouple. External 10nF decoupling capacitor to ground. The voltage on this pin is typically 1.67V when the chip is enabled. The voltage is 0V when the chip is powered down. The purpose of this decoupling capacitor is to filter out low frequency noise (20MHz) on the gain control lines. Poor positioning of the VREF decoupling capacitor can cause a degradation in LO leakage. A voltage of around 2.5V on this pin indicates that the die flag under the chip is not grounded and the chip is not biased correctly. Gain control voltage decouple with an external 1nF decoupling capacitor to ground. The voltage on this pin is a function of gain control (GC) voltage when the chip is enabled. The voltage is 0V when the chip is powered down. The purpose of this decoupling capacitor is to filter out low frequency noise (20MHz) on the gain control lines. The size capacitor on the GC DEC line will effect the settling time response to a step in gain control voltage. A 1nF capacitor equates to around 200ns settling time and a 0.5nF capacitor equates to a 100ns settling time. There is a trade-off between settling time and noise contributions by the gain control circuitry as gain control is applied. Poor positioning of the VREF decoupling capacitor can cause a degradation in LO leakage.
See pin 6.
V CC2
x1
9 10
Q SIG P VREF
See pin 8.
VCC2 4 k
+
11
GC DEC
VCC2 4 k
+
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Rev A1 DS070313
RF3854
Pin 12 Function GC Description
Gain control voltage. Maximum output power at 2.0V. Minimum output power at 0V. When the chip is enabled the input impedance is 10k to 1.67VDC. When the chip is powered down a FET switch is opened and the input goes high impedance.
Interface Schematic
VCC2 4 k 10 k
-
1.7 V
+
13
RF OUT LB N
Differential low band PA driver amplifier output. This output is intended for low band (GSM850/900) operation and drives a differential SAW. A bypass mode allows the low band PA driver amplifier's input to be switched between the signal from the modulator and the signal applied at LOLB. This enables a GMSK-modulated signal on the LOLB input to be switched into the RF signal path. The output is an open collector. The outputs are matched off-chip.
VCC
VCC
VCC
RF OUT LB P RF OUT LB N
14 15
RF OUT LB P RF OUT HB N
Complementary differential low band PA driver amplifier output. See pin 13. Differential high band PA Driver amplifier output. This output is intended for DCS1800/PCS1900 band operation. A bypass mode allows the high band PA driver amplifier's input to be switched between the signal from the modulator and the signal applied at LOHB. This enables a GMSK-modulated DCS1800/PCS1900 signal on the LOHB input to be switched into the RF signal path. The output is an open collector. The outputs are matched off-chip.
See pin 13.
VCC
VCC
VCC
RF OUT HB P RF OUT HB N
16 17
RF OUT HB P RF OUT WB N
Complementary differential high band PA driver amplifier output. See pin 15. Differential high band PA driver amplifier output. This output is intended for wide band (W-CDMA) applications. The output is an open collector. The output are matched off-chip.
See pin 15.
VCC
VCC
VCC
RF OUT WB P RF OUT WB N
18 19
RF OUT WB P GND
Complementary differential wideband PA driver amplifier output. See pin 17. Ground.
See pin 17.
Rev A1 DS070313
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15 of 26
RF3854
Pin 20 21 Function MODE A VCC1 Description
Mode control pin. See the Logic Truth table. CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to VCC. Supply for modulator, VGA and PA driver amplifiers.
Interface Schematic
See pin 6.
VCC1 LO Quadrature Generator and Buffers
GND1
22
I SIG P
23 24 Pkg Base
I SIG N MODE B DIE FLAG
In-phase I channel positive baseband input port. Best performance is achieved when the ISIGP and ISIGN are driven differentially with a 1.2V common mode DC voltage. The recommended differential drive level (VISIGP -VISIGN) is 1.2VP-P for EDGE, 0.8VP-P W-CDMA modulation and 1.0VP-P for GMSK modulation. This input should be DC-biased at 1.2V. In sleep mode an internal FET V switch is opened, the input goes high impedance and the modulator is debiased. Phase or amplitude errors between the ISIGP and ISIGN signals will result x1 in a common-mode signal which may result in an increase in the even order distortion of the modulation in the output spectrum. DC offsets between the ISIGP and ISIGN signals will result in increased carrier leakage. Small DC offsets may be deliberately applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to cancel out the LO leakage. The optimum corrective DC offsets will change with mode, frequency and gain control. Common-mode noise on the ISIGP and ISIGN should be kept low as it may degrade the noise performance of the modulator. Phase offsets from quadrature between the I and Q baseband signals results in degrades sideband suppression. In-phase I channel negative baseband input port. See pin 22. See pin 22.
CC2
Mode control pin. See the Logic Truth table. CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to VCC. Ground for LO section, modular, biasing, variable gain amplifier, and substrate.
See pin 6.
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Rev A1 DS070313
RF3854
LO Frequency Planning Options for European 3GPP W-CDMA/EDGE Recommended Frequency Plan: Frequency Doubler/Divide by 2/GMSK Modulator Bypass Modes Modulation Output Frequency Band LO Port LO Frequency Range Format
Band GSM850 GSM850 GSM900 GSM900 DCS1800 DCS1800 PCS1900 PCS1900 W-CDMA1950 Lower Limit Upper Limit 824MHz 824MHz 880MHz 880MHz 1710MHz 1710MHz 1850MHz 1850MHz 1920MHz 849MHz 849MHz 915MHz 915MHz 1785MHz 1785MHz 1910MHz 1910MHz 1980MHz EDGE 8PSK GSM GMSK EDGE 8PSK GSM GMSK EDGE 8PSK GSM GMSK EDGE 8PSK GSM GMSK 3GPP W-CDMA LOHB LOLB LOHB LOLB LOLB LOHB LOLB LOHB LOLB Lower Limit Upper Limit 1648MHz 824MHz 1760MHz 880MHz 855MHz 1710MHz 925MHz 1850MHz 960MHz 1698MHz 849MHz 1830MHz 915MHz 892.5MHz 1785MHz 955MHz 1910MHz 990MHz FLO/2 Divide by 2 FLO_bypass Bypass, GMSK-modulated LO FLO/2 Divide by 2 FLO_bypass Bypass, GMSK-modulated LO FLOx2 Frequency Doubler FLO_bypass Bypass, GMSK-modulated LO FLOx2 Frequency Doubler FLO_bypass Bypass, GMSK-modulated LO FLOx2 Frequency Doubler
Comments
On Frequency LO with GMSK Modulator Bypass Modes Modulation Output Frequency Band LO Port Format
Band GSM850 GSM850 GSM900 GSM900 DCS1800 DCS1800 PCS1900 PCS1900 W-CDMA1950 Lower Limit Upper Limit 824MHz 824MHz 880MHz 880MHz 1710MHz 1710MHz 1850MHz 1850MHz 1920MHz 849MHz 849MHz 915MHz 915MHz 1785MHz 1785MHz 1910MHz 1910MHz 1980MHz EDGE 8PSK GSM GMSK EDGE 8PSK GSM GMSK EDGE 8PSK GSM GMSK EDGE 8PSK GSM GMSK 3GPP W-CDMA LOLB LOLB LOLB LOLB LOHB LOHB LOHB LOHB LOHB
LO Frequency Range
Lower Limit Upper Limit 824MHz 824MHz 880MHz 880MHz 1710MHz 1710MHz 1850MHz 1850MHz 1920MHz 849MHz 849MHz 915MHz 915MHz 1785MHz 1785MHz 1910MHz 1910MHz 1980MHz
Comments
FLOx1 On Frequency FLO_bypass Bypass, GMSK-modulated LO FLOx1 On Frequency FLO_bypass Bypass, GMSK-modulated LO FLOx1 On Frequency FLO_bypass Bypass, GMSK-modulated LO FLOx1 On Frequency FLO_bypass Bypass, GMSK-modulated LO FLOx1 On Frequency
Rev A1 DS070313
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RF3854
Control Logic Truth Table Mode Description
Mode A Sleep
Wideband FLOx2 (High Power) Modulator and frequency doubler enabled Wideband FLOx2 (Medium Power) Modulator and frequency doubler enabled Wideband FLOx2 (Low Power) Modulator and frequency doubler enabled High Band FLOx2 Modulator and frequency doubler enabled Low Band FLO/2 Modulator and divide by 2 enabled X 1
Input Logic
Mode B
0 0
Active RF I/Os
Mode D
0 0 LoLbP LoLbN RFOutWb P RFOutWb N LoLbP LoLbN RFOutWb P RFOutWb N LoLbP LoLbN RFOutWb P RFOutWb N LoLbP LoLbN RFOutHb P RFOutHb N
Comment
Expected Mode of Operation
Sleep Bands: 1920MHz to 1980MHz Modulation: 3GPP W-CDMA Bands: 1920MHz to 1980MHz Modulation: 3GPP W-CDMA Bands: 1920MHz to 1980MHz Modulation: 3GPP W-CDMA Bands: DCS1800 or PCS1900 Modulation: GMSK, TDMA and 8PSK EDGE
Mode C
0 1
Sleep Mode Frequency Doubler/Divide by 2 Options
1
0
1
1
1
0
0
1
1
1
1
1
1
1
0
1
LoHbP LoHbN Bands: GSM900 or GSM850 RFOutLb P Modulation: GMSK, TDMA and RFOutLb N 8PSK EDGE LoLbP LoLbN RFOutLb P RFOutLb N Bands: GSM850 or GSM900 Modulation: GMSK
GMSK Modulator Bypass Options Low Band Bypass Modulator bypass enabled High Band Bypass Modulator bypass enabled X 1 0 0
X
1
1
0
LoHbP LoHbN Bands: DCS1800 or PCS1900 RFOutHb P Modulation: GMSK RFOutHb N LoHbP LoHbN Bands: 1920MHz to 1980MHz RFOutWb P Modulation: 3GPP W-CDMA RFOutWb N LoHbP LoHbN Bands: 1920MHz to 1980MHz RFOutWb P Modulation: 3GPP W-CDMA RFOutWb N LoHbP LoHbN Bands: 1920MHz to 1980MHz RFOutWb P Modulation: 3GPP W-CDMA RFOutWb N LoHbP LoHbN Bands: DCS1800 or PCS1900 RFOutHb P Modulation: GMSK, TDMA and RFOutHb N 8PSK EDGE LoLbP LoLbN RFOutLb P RFOutLb N Bands: GSM900 to GSM850 Modulation: GMSK, TDMA and 8PSK EDGE
On-Frequency LO Options Wideband FLOx1 (High Power) Modulator and on-frequency LO enabled Wideband FLOx1 (Medium Power) Modulator and on-frequency LO enabled Wideband FLOx1 (Low Power) Modulator and on-frequency LO enabled High Band FLOx1 Modulator and on-frequency LO enabled Low Band FLOx1 Modulator and on-frequency LO enabled 0 0 1 0
0
0
1
1
0
0
0
1
0
1
1
1
0
1
0
1
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Rev A1 DS070313
RF3854
Application Information
The baseband inputs of the RF3854 must be driven with balanced signals. Amplitude and phase matching <0.5dB and <0.5 degrees are recommended. Phase or gain imbalances between the complementary input signals will cause additional distortion including some second order baseband distortion. The RF3854 is designed to be driven with either single-ended or differential LO signals. Driving the chip differentially is beneficial in improving the LO leakage performance. Decreasing the LO drive level will also improve LO leakage, but the output noise performance will be degraded. Driving the LO level too high will degrade linearity. The ground lines for the LO sections are brought out of the chip independently from the ground to the RF and modulator sections. This is intended to give the board design the independence of isolating the LO signals from the RF output sections. The RF3854 includes frequency doubler and divider modes that allow the LO to operate at half or twice the frequency depending on the application. This provides some flexibility in improving VCO isolation and LO leakage through frequency translation. The RF outputs use open collector architecture and may be biased at voltages higher than VCC. In practice, biasing at a higher voltage may improve the intermodulation performance. The load resistors are selected to provide sufficient output power while maintaining good linearity. The GC DEC and VREF output pins should be decoupled to ground. A 10nF capacitor on VREF and a 1nF capacitor on GC CEC are recommended. The purpose of these capacitors is to filter out low frequency noise (20MHz) in the gain control lines that may cause noise on the RF signal. The capacitor on the GC DEC line will effect the settling time of the step response in power control voltage. A 1nF capacitor equates to around a 200ns settling time; a 0.5nF capacitor equates to a 100ns settling time. There is a trade-off between setting time and phase noise as gain control is applied. As with any RF circuit, the RF3854 is sensitive to PC board layout. The suggested schematic and board layout is included as a guideline. Proper grounding of the die flag under the chip is essential in achieving acceptable RF performance. A symmetric output structure will maintain signal balance while keeping the RF lines short will reduce losses. Proper routing and bypassing of the supply lines will improve stability and performance, especially under low gain control settings where carrier suppression becomes crucial. The location and value of the bypass capacitor on pin 1 is critical in promoting good carrier suppression and is designated to resonate out the series wire bond and PC board inductance.
Rev A1 DS070313
7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
19 of 26
RF3854
Package Drawing
4.0
0.10 C
-A-B-
1.00 0.80
4.0
0.10 C B 2 PL 0.10 C A 2 PL 0.2 C
Shaded area indicates pin 1.
Dimensions in mm.
-C-
0.50 TYP
0.10 C A B
0.55 TYP 0.35
SEATING PLANE Scale: None 0.10 C
2.60 2 PL 2.40
0.05 TYP 0.00 0.203 TYP
0.08 C
0.30 TYP 0.18
0.10 M C A B
TYP
0.08 0.03
0.50 TYP 0.30
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Rev A1 DS070313
RF3854
Application Schematic
VCC MODE A VCC
2.2 nH 4.3 pF I SIG P I SIG N MODE B 1 nF 2.2 nH VCC 5.6 pF 1 3.9 nH LO HB 1.8 pF 2
Note: The die flag is the chip's main ground.
T1 1 pF
RF OUT WB
1 k 4.3 pF
2:1 VCC
24
23
22
21
20
19 18 VCC
17
430
4.3 nH T2 1.6 pF RF OUT HB
3 22.0 nH LO LB 3 pF 4
DIV 2
+45 -45
16
1.6 pF 2:1 430 4.3 nH
Flo x2
+45 -45
15
VCC
VCC 5
Mode Control and Biasing Power Control
14 12 nH
MODE C
6 7 8 9 10 11 12
13 1 k
3.3 pF 0.5 pF 3.3 pF
T3
RF OUT LB
MODE D Q SIG N Q SIG P 10 nF 1 nF 12 nH
2:1 VCC
GC
Rev A1 DS070313
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RF3854
Evaluation Board Schematic
VCC MODE A VCC J2 I SIG P J1 I SIG N MODE B C7 12 pF 50 strip
3 2 GND OUT IN 1
50 strip L2 2.2 nH C2 4.3 pF C6 5.6 pF 1 L1 3.9 nH 50 strip 2 C4 1.8 pF 3 L6 22 nH 4 C13 3 pF 5
Mode Control and Biasing Power Control Flo x2
Note: The die flag is the chip's main ground.
J4 WB RF OUT
GND
4
5
R1 1 k
C3 4.3 pF
24
23
22
21
20
19 18
VCC
GND
OUT
J3 HB LO
IN
17 R2 430 16
+45 -45
3
2
1
C11 22 pF
6
GND
50 strip
IN
C1 1 nF
L3 2.2 nH
C12 1.3 pF
T1
Murata LDB211G9020C-001
50 strip
J5 HB RF OUT
DIV 2
-45
4
IN
+45
5
C9 1.6 pF 15
R3 430
C10 1.6 pF
J6 LB LO
50 strip
VCC 14 C8 100 pF 13 7 8 9 10 11 12 L7 12 nH C17 3.3 pF L8 12 nH C16 3.3 pF C18 0.5 pF
4 IN
6
GND
GND
L4 4.3 nH
L5 4.3 nH
C5 DNI
T2
Murata LDB211G8020C-001
50 strip
IN 3 GND 2 OUT 1
6 MODE C MODE D J8 Q SIG N J9 Q SIG P 50 strip C14 10 nF C15 1 nF
J7 LB RF OUT
T3
Murata LDB21906M20C-001
5
R4 1 k
50 strip GC P1-1 P2 1 2 P1-3 3 CON3 VCC GND GC P2-1 P2-2 P2-3 P2-4 P1 1 2 3 MODE D MODE C MODE B
6
GND
GND
MODE A 4 CON4
22 of 26
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Rev A1 DS070313
RF3854
Evaluation Board Layout Board Size 2.250" x 2.250"
Board Thickness 0.032", Board Material FR-4, Multi-Layer
Assembly Top
Mid
Back
Rev A1 DS070313
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RF3854
PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is Electroless Nickel, immersion Gold. Typical thickness is 3inch to 8inch Gold over 180inch Nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern
A = 0.69 x 0.28 (mm) Typ. B = 0.28 x 0.69 (mm) Typ. C = 2.50 (mm) Sq.
Dimensions in mm.
2.50 Typ. 0.50 Typ.
Pin 24
B
Pin 1
B
B
B
B
B
Pin 18
A 0.50 Typ. A A C A A A 0.57 Typ. B B B B B B
A A A 2.50 Typ. A A A 1.25 Typ.
Pin 12
0.57 Typ. 1.25 Typ.
Figure 1. PCB Metal Land Pattern (Top View)
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Rev A1 DS070313
RF3854
PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB Metal Land Pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.79 x 0.38 (mm) Typ. B = 0.38 x 0.79 (mm) Typ. C = 2.60 (mm) Sq. 2.50 Typ. 0.50 Typ.
Pin 24
Dimensions in mm.
B
Pin 1
B
B
B
B
B
Pin 18
A 0.50 Typ. A A C A A A 0.57 Typ. B B B B B B
A A A 2.50 Typ. A A A 1.25 Typ.
Pin 12
0.57 Typ. 1.25 Typ.
Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern shown has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
Rev A1 DS070313
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25 of 26
RF3854
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Rev A1 DS070313

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